1. Field of the Invention
The present invention is directed to an inverter power supply providing from a DC voltage source an oscillation voltage for driving a load and operating with a minimum switching loss.
2. Description of the Prior Art
A prior art inverter power supply is proposed in U.S. Pat. No. 5,225,972. As represented in FIG. 1, the prior power supply comprises a DC voltage source 10', an FET 31', and a transformer 20' having a primary winding 21', a secondary winding 22', and a feedback winding 23'. The primary winding 21' forms a parallel L-C resonant circuit with a capacitor 25'. FET 31' is connected in series with the L-C resonant circuit across the DC voltage source 10' and is driven to turn on and off for causing the L-C resonant circuit to produce an oscillation voltage across the primary winding 21', which in turn produces a corresponding output voltage for driving a load 27' and at the same time to induce a feedback voltage at the feedback winding 23'. The power supply includes a starter circuit composed of a resistor 11' and a biasing capacitor 12' connected in series across the DC voltage source 10'. The biasing capacitor 12' is connected in series with the feedback winding 23' across a source-gate path of FET 31' for providing an offset voltage which is additive to the feedback voltage at the feedback winding 23' to give a bias voltage VG applied to a gate of FET 31' for self-excited oscillation. Further, the power supply includes a bias stabilizing circuit which determines a suitable bias fed to FET 31' at the start of energization of the power supply for assuring to effect subsequent oscillation in a stable manner. The bias stabilizing circuit comprises a resistor 41' and a bypass diode 42' which are connected in series with FET 31' across the biasing capacitor 12' so that, during the ON-period of FET 31', the biasing capacitor 12' is discharged through the bias stabilizing circuit of resistor 41' and diode 42', and through FET 31' to lower the offset voltage of biasing capacitor 12'. At the start of the power supply, the DC voltage source 10' is connected to begin charging biasing capacitor 12' through resistor 11'. When the biasing capacitor 12' is charged to exceed a threshold voltage VTH of FET 31', FET 31' becomes conductive to flow a current through the primary winding 21' with an attendant decrease in a drain voltage VD of FET 31'. Subsequently, when drain voltage VD becomes lower than the voltage of capacitor 12', the bias stabilizing circuit is in operation to discharge the capacitor 12' through resistor 41' and diode 42' and through FET 31', thereby lowering the bias voltage below the threshold voltage VTH to turn off FET 31'. Then, the L-C resonant circuit responds to start providing the oscillation voltage while inducing the corresponding feedback voltage. When the feedback voltage added to the voltage of capacitor 12' increases to such a level that the resulting bias voltage VG exceeds the threshold voltage VTH, FET 31' becomes again conductive to flow the current through the L-C circuit and through FET 31', after which the bias stabilizing circuit acts to lower the bias voltage until FET 31' is turned off. In this manner, the ON-period of FET 31' is gradually reduced with corresponding lowering of the voltage of capacitor 12' until a stable oscillation is reached in which FET 31 is made conductive only for a limited ON-period. That is, the bias voltage is self-adjusted by varying the offset voltage of capacitor 12' in order to assure the stable oscillation with increased efficiency.
However, the prior power supply is found to be still unsatisfactory in minimizing a switching loss due to a certain phenomenon seen in the prior power supply. With the self-excited oscillation utilizing the sinusoidal feedback voltage, it occurs, as shown in FIG. 2, that the bias voltage VG will increase to exceed the threshold voltage VTH shortly before the oscillation voltage, i.e., the drain voltage VD of FET 31' reduces to zero. Consequently, a current I.sub.D is caused to flow through FET 31' within a time interval T.sub.1 prior to the oscillation voltage reduces to zero, resulting in a switching loss and therefore lowering the efficiency of the circuit. In addition, it also occurs that, within a time interval T.sub.2 where the bias voltage exceeds the threshold voltage VTH, the current ID is caused to flow through FET 31' while the oscillation voltage increases above zero, which is also responsible for the switching loss. In other words, the prior power supply fails to effect the switching of FET in coincident as close as possible with the zero voltage of the oscillation voltage and suffers from a certain switching loss and reduced efficiency.